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کد های پروژه
ابتدا کد اصلی:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
— Uncomment the following library declaration if using
— arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
— Uncomment the following library declaration if instantiating
— any Xilinx leaf cells in this code.
–library UNISIM;
–use UNISIM.VComponents.all;
entity ALU is
Port (
clk : in std_logic;
newvalue :in STD_LOGIC;
a : in STD_LOGIC_VECTOR (32-1 downto 0);
alucontroler : in STD_LOGIC_VECTOR (3-1 downto 0);
b : in STD_LOGIC_VECTOR (32-1 downto 0);
z : out STD_LOGIC;
o : out STD_LOGIC;
n : out STD_LOGIC;
rdy : out STD_LOGIC;
c : out STD_LOGIC;
y : out STD_LOGIC_VECTOR (32-1 downto 0));end ALU;
architecture Behavioral of ALU is
component multi_16 is
Port (
clk : in STD_LOGIC;
a : in std_logic_vector(32-1 downto 0 );
b : in std_logic_vector(32-1 downto 0 );
start : in std_logic;
rdy : out std_logic;
o : out std_logic_vector(32-1 downto 0 )
);end component;
signal add_op : std_logic_vector(33-1 downto 0) :=( others=>’0′);
signal sub_op : std_logic_vector(33-1 downto 0) :=( others=>’0′);
signal mult_op : std_logic_vector(32-1 downto 0) :=( others=>’0′);
signal slt_op : std_logic_vector(32-1 downto 0) :=( others=>’0′);
signal And_Op : std_logic_vector(32-1 downto 0) :=( others=>’0′);
signal or_op : std_logic_vector(32-1 downto 0) :=( others=>’0′);
signal xor_op : std_logic_vector(32-1 downto 0) :=( others=>’0′);
signal out_put : std_logic_vector(32-1 downto 0) :=( others=>’0′);
signal start : std_logic := ‘0’ ;
signal rdy_m : std_logic := ‘0’ ;
signal i : integer := 0 ;
signal a2 : signed (32-1 downto 0);
signal b2 : signed (32-1 downto 0);
begin
inst_mult: multi_16
Port map (
clk => clk,
a => a,
b => b,
start => start,
rdy => rdy_m,
o => mult_op
);
add_op <= std_logic_vector(signed(a(31) & a) + signed(b(31) & b) );
sub_op <= std_logic_vector(signed(a(31) & a) – signed(b(31) & b ) );
a2 <= signed (a);
b2 <= signed (b);
slt_op <= x”0000000″ & “0001” when (signed(a) < signed(b)) else x”00000000″ ;
And_Op <= a and b ;
or_op <= a or b ;
xor_op <= a xor b ;
process (clk)
begin
if ( rising_edge (clk)) then
z <= '0';
o <= '0';
n <= '0';
c <= '0';
rdy <= '0';
---
if (newvalue = '1' ) then
i <= 1;
end if;
if i = 1 then
case (alucontroler) is
when "000" => -- NOp
y <= x"00000000";
z <= '0';
o <= '0';
c <= '0';
n <= '0';
rdy <= '1';
i <= 0;
when "001" => -- Add
y <= add_op(32-1 downto 0);
rdy <= '1';
i <= 0;
if ( signed (add_op(32-1 downto 0)) /= signed(add_op)) then --( signed (add_op(32-1 downto 0)) /= signed(add_op) (a(31) = '0' and b(31) = '0'and add_op(31) = '1')
o <= '1' ;
end if;
if add_op(32) = '1' then
c <= '1' ;
end if ;
if add_op(32-1 downto 0) = x"00000000" then
z <= '0';
end if;
if add_op(31) = '1' then
n <= '1' ;
end if;
when "010" => -- Sub
y <= sub_op(32-1 downto 0);
rdy <= '1';
i <= 0;
if ( signed (sub_op(32-1 downto 0)) /= signed(sub_op)) then
o <= '1' ;
end if;
if sub_op(32-1 downto 0) = x"00000000" then
z <= '0';
end if;
if sub_op(31) = '1' then
n <= '1' ;
end if;
when "011" => -- Mult
start <= '1' ;
if rdy_m ='1' then
y <= mult_op ;
rdy <= '1';
start <= '0';
i <= 0;
if mult_op(32-1 downto 0) = x"00000000" then
z <= '0';
end if;
-- if mult_op(31) = '1' then
-- n <= '1' ;
-- end if;
end if;
-- if mult_op (32) = '1' then
-- o <= '1' ;
-- end if;
when "100" => -- Slt
y <= slt_op;
rdy <= '1';
i <= 0;
rdy <= '1';
-- if slt_op (32) = '1' then
-- o <= '1' ;
--end if;
if slt_op(32-1 downto 0) = x"00000000" then
z <= '0';
end if;
if slt_op(31) = '1' then
n <= '1' ;
end if;
when "101" => -- And
y <= And_Op;
rdy <= '1';
i <= 0;
rdy <= '1';
-- if And_Op (32) = '1' then
-- o <= '1' ;
--end if;
if And_Op(32-1 downto 0) = x"00000000" then
z <= '0';
end if;
-- if And_Op(31) = '1' then
-- n <= '1' ;
-- end if;
when "110" => -- Or
y <=or_op ;
rdy <= '1';
i <= 0;
rdy <= '1';
-- if or_op (32) = '1' then
-- o <= '1' ;
--end if;
if or_op(32-1 downto 0) = x"00000000" then
z <= '0';
end if;
-- if or_op(31) = '1' then
-- n <= '1' ;
-- end if;
when "111" => -- Xor
y <= xor_op ;
rdy <= '1';
i <= 0;
rdy <= '1';
--- if xor_op (32) = '1' then
-- o <= '1' ;
-- end if;
if xor_op(32-1 downto 0) = x"00000000" then
z <= '0';
end if;
-- if xor_op(31) = '1' then
-- n <= '1' ;
-- end if;
when others => -- defalt value
z <= '0';
o <= '0';
n <= '0';
rdy <= '0';
i <= 0;
end case;
end if;
end if;
end process;
end Behavioral;
تست بنج
— Company:
— Engineer:
— Create Date: 05/23/2024 04:25:08 AM
— Design Name:
— Module Name: sim_ALu – Behavioral
— Project Name:
— Target Devices:
— Tool Versions:
— Description:
— Dependencies:
— Revision:
— Revision 0.01 – File Created
— Additional Comments:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
— Uncomment the following library declaration if using
— arithmetic functions with Signed or Unsigned values
–use IEEE.NUMERIC_STD.ALL;
— Uncomment the following library declaration if instantiating
— any Xilinx leaf cells in this code.
–library UNISIM;
–use UNISIM.VComponents.all;
entity sim_ALu is
end sim_ALu;
architecture Behavioral of sim_ALu is
component ALU is
Port (
clk : in std_logic;
newvalue :in STD_LOGIC;
a : in STD_LOGIC_VECTOR (32-1 downto 0);
alucontroler : in STD_LOGIC_VECTOR (3-1 downto 0);
b : in STD_LOGIC_VECTOR (32-1 downto 0);
z : out STD_LOGIC;
o : out STD_LOGIC;
n : out STD_LOGIC;
rdy : out STD_LOGIC;
c : out STD_LOGIC;
y : out STD_LOGIC_VECTOR (32-1 downto 0));end component;
signal clk : std_logic;
signal newvalue : STD_LOGIC;
signal a : STD_LOGIC_VECTOR (32-1 downto 0);
signal alucontroler : STD_LOGIC_VECTOR (3-1 downto 0);
signal b : STD_LOGIC_VECTOR (32-1 downto 0);
signal z : STD_LOGIC;
signal o : STD_LOGIC;
signal n : STD_LOGIC;
signal rdy : STD_LOGIC;
signal c : STD_LOGIC;
signal y : STD_LOGIC_VECTOR (32-1 downto 0);
constant clk_period : time := 10 ns;
begin
inst_ALU: ALU
Port map (
clk =>clk,
newvalue => newvalue,
a => a,
alucontroler => alucontroler,
b =>b,
z =>z,
o =>o,
n =>n,
rdy =>rdy,
c =>c,
y =>y
);— Clock process definitions
clk_process :process
begin
clk <= ‘0’;
wait for clk_period/2;
clk <= ‘1’;
wait for clk_period/2;
end process;
-- Stimulus processstim_proc: process
begin
— test nop
newvalue <= ‘1’;
a <=”01100011100001001001001111011000″;
b <= “10000100110001101100100110010001”;
wait for clk_period ;
newvalue <= ‘0’;
alucontroler <= “000”;
wait for 20 * clk_period ;
— test add 1
newvalue <= ‘1’;
a <= “01111111111111111111111111111111”;
b <= “01111111111111111111111111111111”;
wait for clk_period ;
newvalue <= ‘0’;
alucontroler <= “001”;
wait for 20 * clk_period ;
— test add 2
newvalue <= ‘1’;
a <= “11111111111111111111111111111111”;
b <= “11111111111111111111111111111111”;
wait for clk_period ;
newvalue <= ‘0’;
alucontroler <= “001”;
wait for 20 * clk_period ;
— test sub
newvalue <= ‘1’;
a <=”00000110010000010000110101110001″;
b <= “00000110010000010111001100000001”;
wait for clk_period ;
newvalue <= ‘0’;
alucontroler <= “010”;
wait for 20 * clk_period ;
— test mult
newvalue <= ‘1’;
a <= “00000000000000001111111111111111”;
b <= “00000000000000001111111111111111”;
wait for clk_period ;
newvalue <= ‘0’;
alucontroler <= “011”;
wait for 20 * clk_period ;
— test slt
newvalue <= ‘1’;
a <=”00000000000000001011110101110001″;
b <= “00000000000000001100110111011011”;
wait for clk_period ;
newvalue <= ‘0’;
alucontroler <= “100”;
wait for 20 * clk_period ;
— test and
newvalue <= ‘1’;
a <=”10101001011001101011110101110001″;
b <= “10010101110001101100110111011011”;
wait for clk_period ;
newvalue <= ‘0’;
alucontroler <= “101”;
wait for 20 * clk_period ;
— test or
newvalue <= ‘1’;
a <=”10101001011001101011110101110001″;
b <= “10010101110001101100110111011011”;
wait for clk_period ;
newvalue <= ‘0’;
alucontroler <= “110”;
wait for 20 * clk_period ;
— test xor
newvalue <= ‘1’;
a <=”10101001011001101011110101110001″;
b <= “10010101110001101100110111011011”;
wait for clk_period ;
newvalue <= ‘0’;
alucontroler <= “111”;
wait for 20 * clk_period ;
wait;
end process;
end Behavioral;
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