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توضیحات
کد های این پروژه
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity multiplier_phase1 is
Port ( a : in STD_LOGIC_vector(31 downto 0);
b : in STD_LOGIC_vector(31 downto 0);
y : out STD_LOGIC_vector(31 downto 0);
start : in std_logic;
ready : out std_logic;
clk : in STD_LOGIC);
end multiplier_phase1;
architecture Behavioral of multiplier_phase1 is
signal product : std_logic_vector(31 downto 0):= (others =>’0′);
signal multiplicand : std_logic_vector(31 downto 0) :=(others =>’0′);
signal multiplier : std_logic_vector(15 downto 0) := (others =>’0′);
signal in_product : std_logic_vector(31 downto 0) := (others =>’0′);
signal counter : integer := 1;
type state1 is (idle, multiply);
signal state : state1 := idle;
begin
in_product <= multiplicand + product ; y <= product; process (clk) begin if rising_edge(clk) then case state is when idle =>
ready <= ‘0’; if start = ‘1’ then multiplier <= b(15 downto 0); multiplicand <= (“0000000000000000”) & a(15 downto 0); product <= (others =>’0′);
state <= multiply; else state <= idle; end if; when multiply =>
if counter <17 then
multiplier <= ‘0’ & multiplier(15 downto 1);
multiplicand <= multiplicand(30 downto 0) & ‘0’;
counter <= counter +1;
if multiplier(0) = ‘1’ then
product <= in_product;
end if;
elsif counter = 17 then
ready <= ‘1’;
counter <= 1;
state <= idle;
end if;
end case;
end if;
end process;
end Behavioral;
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تست :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multiplier_phase1_tb is
— Port ( );
end multiplier_phase1_tb;
architecture Behavioral of multiplier_phase1_tb is
component multiplier_phase1 is
Port ( a : in STD_LOGIC_vector(31 downto 0);
b : in STD_LOGIC_vector(31 downto 0);
y : out STD_LOGIC_vector(31 downto 0);
start : in std_logic;
ready : out std_logic;
clk : in STD_LOGIC);
end component;
constant clkperiod : time := 100ns;
signal a : std_logic_vector(31 downto 0);
signal b : std_logic_vector(31 downto 0);
signal clk : std_logic;
signal start : std_logic;
signal ready : std_logic;
signal y : std_logic_vector(31 downto 0);
begin
multiplier_testbench : multiplier_phase1
port map (
a => a ,
b => b ,
clk => clk ,
start=> start,
ready=> ready,
y => y
);
process
begin
————————————————1st test———————————————-
a <= x”00001234″;
b <= x”00005678″;
clk <= ‘1’;
wait for clkperiod/2;
clk <= ‘0’;
wait for clkperiod/2;
start <= ‘1’;
clk <= ‘1’;
wait for clkperiod/2;
clk <= ‘0’;
wait for clkperiod/2;
start <= ‘0’;
for i in 1 to 20 loop
clk <= ‘1’;
wait for clkperiod/2;
clk <= ‘0’;
wait for clkperiod/2;
end loop;
————————————————2nd test———————————————-
a <= x”00002acb”;
b <= x”00008301″;
start <= ‘1’;
clk <= ‘1’;
wait for clkperiod/2;
clk <= ‘0’;
wait for clkperiod/2;
start <= ‘0’;
for i in 1 to 20 loop
clk <= ‘1’;
wait for clkperiod/2;
clk <= ‘0’;
wait for clkperiod/2;
end loop;
————————————————3rd test———————————————-
a <= x”00001ff0″;
b <= x”0000982c”;
start <= ‘1’;
clk <= ‘1’;
wait for clkperiod/2;
clk <= ‘0’;
wait for clkperiod/2;
start <= ‘0’;
for i in 1 to 20 loop
clk <= ‘1’;
wait for clkperiod/2;
clk <= ‘0’;
wait for clkperiod/2;
end loop;
wait;
end process;
end Behavioral;
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نوع 2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
— Uncomment the following library declaration if using
— arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
— Uncomment the following library declaration if instantiating
— any Xilinx leaf cells in this code.
–library UNISIM;
–use UNISIM.VComponents.all;
entity multi_16 is
Port (
clk : in STD_LOGIC;
a : in std_logic_vector(32-1 downto 0 );
b : in std_logic_vector(32-1 downto 0 );
start : in std_logic;
rdy : out std_logic;
o : out std_logic_vector(32-1 downto 0 )
);end multi_16;
architecture Behavioral of multi_16 is
signal Multiplier : std_logic_vector (16-1 downto 0):= (others => ‘0’);
signal Multiplicand : std_logic_vector (32-1 downto 0);
signal product : std_logic_vector (32-1 downto 0):= (others => ‘0’);
signal i,x : integer:= 0 ;
begin
process ( clk)
begin
if( rising_edge(clk)) then
rdy <= ‘0’ ;
if(start ='1' ) and x= 0 then
Multiplier <= a(16-1 downto 0) ;
Multiplicand <= x"0000" & b(16-1 downto 0);
x <= 1 ;
end if;
if x = 1 then
-- shfts of Multiplicand & Multiplier
Multiplier <= '0' & Multiplier(16-1 downto 1);
Multiplicand <= Multiplicand (32-2 downto 0) & '0' ;
if (Multiplier(0) = '1') then
product <= std_logic_vector (unsigned(Multiplicand) + unsigned(product));
i <= i+1;
else
i<= i+1;
end if;
if i = 16 then
rdy <= '1';
o <= product;
product <= x"00000000";
i <= 0;
x <= 0;
end if;
end if;
end if;
end process;
end Behavioral;
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تست:
–
use IEEE.STD_LOGIC_1164.ALL;
— Uncomment the following library declaration if using
— arithmetic functions with Signed or Unsigned values
–use IEEE.NUMERIC_STD.ALL;
— Uncomment the following library declaration if instantiating
— any Xilinx leaf cells in this code.
–library UNISIM;
–use UNISIM.VComponents.all;
entity sim_mult is
end sim_mult;
architecture Behavioral of sim_mult is
signal o :std_logic_vector(32-1 downto 0);
signal rdy :std_logic;
signal start :std_logic;
signal b :std_logic_vector(32-1 downto 0 );
signal a :std_logic_vector(32-1 downto 0 );
signal clk :STD_LOGIC;
constant clk_period : time := 10 ns;
component multi_16 is
Port (
clk : in STD_LOGIC;
a : in std_logic_vector(32-1 downto 0 );
b : in std_logic_vector(32-1 downto 0 );
start : in std_logic;
rdy : out std_logic;
o : out std_logic_vector(32-1 downto 0 )
);end component;
begin
inst_mult: multi_16
Port map (
clk => clk,
a => a,
b => b,
start => start,
rdy => rdy,
o => o
);— Clock process definitions
clk_process :process
begin
clk <= ‘0’;
wait for clk_period/2;
clk <= ‘1’;
wait for clk_period/2;
end process;
— Stimulus process
stim_proc: process
begin
a <= x"00000007" ;
b <= x"00000005";
wait for 4* clk_period ;
start <= '1' ;
wait for clk_period ;
start <= '0' ;
wait for 20* clk_period ;
a <= x"0000ffff" ;
b <= x"0000ffff";
wait for 4* clk_period ;
start <= '1' ;
wait for clk_period ;
start <= '0' ;
wait for 20* clk_period ;
wait;
end process;end Behavioral;